Structure and method of high performance two layer ball grid array substrate

ABSTRACT

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.

FIELD OF THE INVENTION

The present invention is related in general to the field ofsemiconductor devices and processes and more specifically to structure,materials and fabrication of high performance plastic ball-grid arraypackages designed for flip-chip assembly.

DESCRIPTION OF THE RELATED ART

Ball Grid Array (BGA) packages have emerged as an excellent packagingsolution for integrated circuit (IC) chips with high input/output (I/O)count. BGA packages use sturdy solder balls for surface mount connectionto the “outside world” (typically plastic circuit boards, PCB) rathersensitive package leads, as in Quad Flat Packs (QFP), Small OutlinePackages (SOP), or Tape Carrier Packages (TCP). Some BGA advantagesinclude ease of assembly, use of surface mount process, low failure ratein PCB attach, economic use of board area, and robustness underenvironmental stress. The latter used to be true only for ceramic BGApackages, but has been validated in the last few years even for plasticBGAs. From the standpoint of high quality and reliability in PCB attach,BGA packages lend themselves much more readily to a six-sigma failurerate fabrication strategy than conventional devices with leads to besoldered.

A BGA package generally includes an IC chip, a multi-layer substrate,and a heat spreader. The chip is generally mounted on the heat spreaderusing a thermally conductive adhesive, such as an epoxy. The heatspreader provides a low resistance thermal path to dissipate thermalenergy, and is thus essential for improved thermal performance duringdevice operation, necessary for consistently good electricalperformance. The heat spreader is generally construed of copper and mayinclude gold plating—representing an expensive part of the package.Further, the heat spreader provides structural and mechanical support byacting as a stiffener, adding rigidity to the BGA package, and may thusbe referred to as a heat spreader/stiffener.

One of the substrate layers includes a signal “plane” that providesvarious signal lines, which can be coupled, on one end, to acorresponding chip bond pad using a wire bond (or to a contact pad usingflip-chip solder connection). On the other end, the signal lines arecoupled with a solder “ball” to other circuitry, generally through aPCB. These solder balls form the array referred to in a BGA.Additionally, a ground plane will generally be included on one of thesubstrate layers to serve as an active ground plane to improve overalldevice performance by lowering the inductance, providing controlledimpedance, and reducing cross talk. These features become the moreimportant the higher the BGA pin count is.

In contrast to the advantages of the BGA packages, prevailing solutionsin BGA packages have lagged in performance characteristics such as powerdissipation and the ability to maintain signal integrity in high speedoperation necessary for devices such as high speed digital signalprocessors (DSP) and mixed signal products (MSP). Electrical performancerequirements are driving the need to use multi-layer copper-laminatedresin substrates (previously ceramic). As clock frequencies and currentlevels increase in semiconductor devices, the packaging designs arechallenged to provide acceptable signal transmission and stable powerand ground supplies. Providing stable power is usually achieved by usingmultiple planes in the package, properly coupled to one another and tothe signal traces. In many devices, independent power sources are neededfor core operation and for output buffer supply but with a common groundsource.

As for higher speeds, flip chip assembly rather than wire bonding hasbeen introduced. Compared to wire bonding within the same packageoutline, flip chip assembly offers greatly reduced IR drop to thesilicon core circuits; significant reduction of power and groundinductances; moderate improvement of signal inductance; moderatedifference in peak noise; and moderate reduction in pulse widthdegradation.

In order to satisfy all these electrical and thermal performancerequirements, packages having up to eight metal layers have beenintroduced. The need, however, of high numbers of layers is contrary tothe strong market emphasis on total semiconductor device package costreduction. This emphasis is driving an ongoing search forsimplifications in structure and materials, of course with theconstraint that electrical, thermal and mechanical performances shouldbe affected only minimally.

The complexity and cost of the BGA packages are also influenced by thenumber of interconnections or vias that must be fabricated in thesubstrate layers to provide a path to connect each of the solder ballsto either the ground plane, the power planes, or desired signal lines ofthe signal plane. Each via requires the formation of an electricallyconductive layer on the internal walls of the via, to ensure a completeelectrical path. Generally, the metallization of the internal walls ofeach via increases the overall complexity. Consequently, multiple viasand multiple substrate layers result not only in higher BGA fabricationcosts, but also lower yields.

Analyzing the total package cost shows that the cost of the substratedominates (usually more than 50%), followed by the heat slug (usually atleast 30%). In order to reduce the substrate cost, however, the numberof layers should be reduced. This approach, in turn, seems to greatlyendanger the electrical and thermal package performance.

An urgent need has therefore arisen to break this vicious cycle andconceive a concept for a low-cost, yet high performance BGA packagestructure. Preferably, this structure should be based on a fundamentaldesign concept flexible enough to be applied for different semiconductorproduct families and a wide spectrum of design and assembly variations.It should not only meet high electrical and thermal performancerequirements, but should also achieve improvements towards the goals ofenhanced process yields and device reliability. Preferably, theseinnovations should be accomplished using the installed equipment base sothat no investment in new manufacturing machines is needed.

SUMMARY OF THE INVENTION

According to the present invention, a high-performance, highinput/output ball grid array substrate is provided, which is designedfor integrated circuit flip-chip assembly and has two patterned metallayers and an intermediate insulating layer.

The insulating layer has a plurality of vias filled with metal, and oneof the metal layers attached to each surface. Positioned between the twometal layers, the insulating layer has a thickness and materialcharacteristics suitable for strong electromagnetic coupling between thesignal lines and the first metal layer. In this manner, a predeterminedimpedance to ground is provided, and cross-talk between signal lines isminimized.

The first metal layer provides the electrical ground potential and has aplurality of electrically insulated openings for outside electricalcontacts.

The second metal layer has three portions: The first portion isconfigured as a plurality of signal lines; the second portion isconfigured as a plurality of first electrical power lines operable at afirst potential; and the third portion is configured as a plurality ofsecond electrical power lines operable at a second potential. The firstpower lines are configured so wide that their combined inductancesapproximate the inductance of a metal having the size of the totalsubstrate. The second power lines are configured to serve as distributedareas having wide geometries for minimizing self-inductance and merginginto a central area supporting the IC chip.

It is an aspect of the invention that the signal lines are distributedrelative to the first power lines such that the inductive couplingbetween them reaches at least a minimum value, providing high mutualinductances and close to zero effective self-inductance. Further, thesignal lines are electromagnetically coupled to the ground metal suchthat cross-talk between signal lines is minimized.

Another aspect of the invention is to provide an outermost insulatinglayer protecting the exposed surface of the ground layer. Thisinsulating film has a plurality of openings filled with metal suitablefor solder ball attachment.

Another aspect of the invention is to provide another outermostinsulating layer protecting the exposed surfaces of the signal and powerlines. This insulating film has a plurality of openings filled withmetal suitable for contacting selected signal and ground lines and chipsolder bumps.

Another aspect of the invention is to provide the modeling guidelinesfor designing the substrate structures and materials such that they areflexible enough to be applied for different semiconductorhigh-performance device families and a wide spectrum of high speed, highpower design and assembly variations.

Another aspect of the invention is to utilize existing semiconductorfabrication processes and to reach the substrate and device goalswithout the cost of equipment changes and new capital investment, byusing the installed fabrication equipment.

Another aspect of the invention is to reduce the thickness of the BGAsubstrate substantially so that the BGA device can readily be employedin a variety of new products requiring thin semiconductor components.

Another aspect of the invention is to improve the inherent thermaldissipation to a degree that the use of a heat slug is no longermandatory to achieve the required thermal characteristics.

These aspects have been achieved by the computer-implemented method formodeling a high-performance, high I/O ball grid array substrate, and bya method for fabricating this substrate for integrated circuit flip-chipassembly, suitable for mass production.

The technical advances represented by the invention, as well as theaspects thereof, will become apparent from the following description ofthe preferred embodiments of the invention, when considered inconjunction with the accompanying drawings and the novel features setforth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic and simplified cross section of the Ball GridArray device having a substrate according to the invention.

FIG. 2 is a simplified perspective view of the first and the secondmetal layers.

FIG. 3 is a simplified perspective view of the first metal layer asviewed from the bottom.

FIG. 4 is a simplified top view of a portion of the second metal layer,showing the structure of the signal lines.

FIG. 5 is a simplified top view of a portion of the second metal layer,showing the structure of the first power lines.

FIG. 6 is a simplified top view of a portion of the second metal layer,showing the structure of the second power lines.

FIG. 7 is a simplified top view of the second metal layer showing thecombined structures of signal lines, first power lines, and second powerlines.

FIG. 8 is a flowchart illustrating an exemplary computer-implementedmethod for electrically modeling the structure of the metal and powerlines according to the teachings of the present invention.

FIG. 9 is a flowchart illustrating an exemplary method for forming aball grid array package substrate according to the teachings of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a simplified and schematic cross sectional view of a portionof the high-performance, high input/output (I/O) Ball Grid Array (BGA)package of the invention, generally designated 100. Using solder bumps102 in flip-chip technology, the active surface 101 a of the integratedcircuit chip 101 is attached to openings in the outermost insulatingfilm 111 of substrate 110, facing the active chip surface 101 a. Chip101 is commonly made of silicon and has a thickness typically in therange of about 200 to 375 μm. The number of I/O's typically is in therange from about 100 to 600; approximately one half of these I/O's servesignal lines, the other half is dedicated to power and groundpotentials.

The solder bumps 102 connecting the chip I/O's to the substrate 110 areusually small in diameter, typically about 100 to 120 μm with a range of±10 μm, and comprise attach materials selected from a group consistingof tin, lead/tin alloys, indium, indium/tin alloys, solder paste, andconductive adhesive compounds. Following the flip-chip attachment, anygaps between chip 101 and substrate 110, and also between the solderbumps 102, are filled with a polymeric encapsulant 103. This encapsulanttypically is a polymeric precursor mad of an epoxy base material filledwith silica and anhydrides, requiring thermal energy for curing to forma polymeric encapsulant.

The encapsulation material 104, surrounding the chip 101 after flip-chipattachment, serves the protection of the mounted chip. Commonly, it is apolymeric material selected from a group consisting of epoxy-basedmolding compounds suitable for adhesion to the chip, andfluoro-dielectric compounds supporting high-speed and high-frequencypackage performance. For molding compounds, standard transfer moldingprocesses are the preferred method of encapsulation in mass fabrication.Over the passive surface 101 b of the chip, the molded material 104 amay have a thickness typically in the range from 300 to 500 μm, betweenthe substrate and the heat slug from about 500 to 800 μm.

The heat spreader 105, positioned on the outer surface of theencapsulation material 104, is optional. Its thickness is typically inthe range from about 150 to 300 μm. It enhances heat spreading and heatdissipation and thus the overall thermal performance of the devicesignificantly, but is usually made of copper and thus a substantial costcontributor. However, based on the outstanding thermal characteristicsof the BGA substrate of the present invention, the desired thermaldevice performance can be achieved even without an additional heatspreader.

Solder balls 106 are attached to the plurality of openings in theoutermost insulating film 112 of substrate 110. As defined herein, theterm solder “balls” does not imply that the solder contacts arenecessarily spherical. They may have various forms, such assemispherical, half-dome, truncated cone, or generally bump. The exactshape is a function of the deposition technique (such as evaporation,plating, or prefabricated units) and reflow technique (such as infraredor radiant heat), and the material composition. The solder balls usuallyhave a diameter in the range from about 0.1 to 0.4 mm. Several methodsare available to achieve consistency of geometrical shape by controllingamount of material and uniformity of reflow temperature. The solderballs 106 comprise attach materials selected from a group consisting oftin/lead, tin/indium, tin/silver, tin/bismuth, solder paste, andconductive adhesive compounds.

The two outermost insulating films 111 and 112 of the substrate serve asprotection for the substrate metal patterns and as solder masks. Thefilms preferably are glass-filled epoxies, polyimides, acrylics or otherphoto-imageable materials suitable as solder masks in the thicknessrange from about 50 to 100 μm. The openings for solder bump and solderball attachments are made of copper including a flash of gold, palladiumor platinum, or other wettable and solderable metals.

As FIG. 1 schematically shows, the substrate 110 consists of aninsulating layer 113 having a first surface 113 a, a second surface 113b, and a plurality of vias 114 filled with metal. The preferred metal iscopper, but tungsten or any other electrically conductive materials aresuitable. The insulating layer 113 has preferably a thickness in therange from about 70 to 150 μm and is made of organic material selectedfrom a group consisting of polyimide, polymer strengthened by glassfibers, FR-4, FR-5, and BT resin. The dielectric constant is preferablybetween 4 and 5.

Attached to the first substrate surface 113 a is a metal layer 115,configured to provide electrical ground potential. Attached to thesecond surface 113 b is a metal layer 116, configured to provide aplurality of electrical signal lines, further a plurality of firstelectrical power lines, and further a plurality of second electricalpower lines. The total thickness of the substrate 110 is preferably inthe range from about 150 to 300 μm.

The two metal layers 115 and 116 have a thickness preferably in therange of about 7 to 15 μm, and are made, for example, of copper, brass,aluminum, silver, or alloys thereof. Metal layer 115, herein called the“first metal layer”, is designed to provide the electrical groundpotential. It has a plurality of openings, each having an electricallyinsulated ring and metal in the core for outside electrical contacts.This core metal is solderable and connects to the solder balls 106.

Metal layer 116, herein called the “second metal layer”, is designed sothat a portion is configured as a plurality of electrical signal lines,a further portion as a plurality of first electrical power lines, and afinal portion as a plurality of second electrical power lines. Theseportions are illustrated in more detail in FIGS. 4 to 7.

The relation and position of the two metal layers are shown inperspective view in FIGS. 2 and 3. Layer 210 is the first metal layer,providing the electrical ground potential. The plurality of openings isdesignated 211. When layer 210 is viewed perspectively from theunderside, as illustrated in FIG. 3, a plurality of solder balls 311 isattached to the plurality of openings. Solder balls 311 establish theconnections of the BGA to the outside world.

Referring now to FIG. 2, layer 220 is the second metal layer, providingthe plurality of signal lines 221, first power lines 222 and secondpower lines 223. In the center of the second metal layer 220 is theflip-chip attach area 224, with the larger portion of the metalbelonging to the second power lines. More detail is displayed in FIGS. 4to 7.

FIG. 4 shows one quadrant, generally designated 400, of the signal lineportion of the second metal layer 116. The total signal line portion hasthree additional quadrants of similar configuration. An individualsignal line 401 has a width between 25 and 60 μm. One signal line isspaced to the adjacent signal line by insulating material of a widthfrom about 20 to 50 μm. As FIG. 4 shows, the signal lines terminate atinner endpoints 402 close to the periphery of the chip-to-be-attached,preferably in two staggered rows 402 a and 402 b of staggered endpoints.The outer endpoints 403 fan out wide in order to serve a distributedarray of solder ball connections.

FIG. 5 shows one quadrant, generally designated 500, of the portion ofthe first power lines of the second metal layer 116. The total portionof the first power lines has three additional quadrants of similarconfiguration. An individual power line 501 has a width from about 200to 500 μm. It is an important aspect of the present invention that thatthe first power lines are configured so wide that their combinedinductances approximate the inductance of a metal which would have thesize of the total substrate. As FIG. 5 shows, the first power linesterminate at inner endpoints 502 close to the periphery of thechip-to-be-attached. The outer endpoints 503 fan out wide in order toserve a distributed array of solder ball connections. By way of example,the first power lines may be at an applied potential of 3.0 V.

It is further an important aspect of the present invention that thesignal lines of FIG. 4 are positioned in a proximity of about 20 to 50μm to the first power lines of FIG. 5, thus providing strongelectromagnetic coupling, high mutual inductance and minimized effectiveself-inductance.

It is further an important aspect of the present invention that thesignal lines are positioned to provide strong electromagnetic couplingto power and ground lines and thus minimal coupling, or cross-talk,between the signal lines.

It is further an important aspect of the present invention that thesignal lines are distributed relative to the first power lines such thatthe inductive coupling between them reaches at least a minimum value,providing high mutual inductances and minimized effectiveself-inductance.

FIG. 6 shows all four quadrants, generally designated 600, of theportion of the second power lines of the second metal layer. Thesesecond power lines are structured as distributed areas 601 having widegeometries for minimizing self-inductance; these areas may, forinstance, utilize the four corners of the package. The second powerlines merge into a central area 602 supporting a large number of chipsolder bumps. By way of example, the second power lines may be at a 1.8V applied potential.

In FIG. 7, the three portions of the second metal layer, detailed inFIGS. 4, 5 and 6, are combined and displayed for one quadrant in orderto illustrate the complex interrelated positioning of the signal lines,first power lines, and second power lines according to the invention.The three remaining quadrants of the first metal structures, not shownin FIG. 7, are analogous to the one quadrant shown relative to thecombination of signal and first power lines.

FIG. 8 is a flowchart illustrating an exemplary computer-implementedmethod 800 for modeling a high-performance, high I/O ball grid arraysubstrate for IC flip-chip assembly according to the teachings of thepresent invention. Method 800 begins at step 802 by collecting theinputs of a first and a second metal layer, all of substantially equalareas. The first metal layer provides electrical ground potential.

The majority of the modeling concerns the three portions of the secondmetal layer. The method proceeds next to step 804 where the I/O count ofthe signal lines of the second metal layer is determined. With the I/Oinput at step 806, the widths and layout of the signal lines areselected. Based on this selection, the resulting impedance levels of thesignal lines are modeled at step 808. Further, the signal lines areelectromagnetically coupled to the ground potential applied to the firstmetal layer; using this coupling, the cross talk between the signallines is modeled with the goal of minimizing the cross talk.

At step 810, details of the first power lines (operable at a firstelectrical potential, for instance 3.0 V) of the second metal layer areadded to the modeling. The plurality of the signal lines is routed inconjunction with the plurality of the first power lines with the goal ofproviding at least a minimum inductive coupling between signal and powerlines. This goal strives to obtain high mutual inductance and tominimize effective self-inductance. If the result of this modeling stepis not satisfactory, the widths of the signal lines are modified in step809. They are fed back as improved inputs to step 808 in order to repeatthe impedance modeling, and then to step 810 in order to repeat thesignal and power lines routing and distribution.

After completing the relative positioning of signal and first powerlines, achieving high mutual inductances and minimized effectiveself-inductance, the widths of the first power lines are maximized instep 812. The goal is to configure the first power lines so wide thattheir combined inductances approximates the inductance of a metal havingthe area size of the total substrate.

At steps 814 and 816, the coupling between signal lines and first powerlines is further modeled, especially by simulating electrical noise. Ifthe relative line distribution does not exhibit enough insensitivity orsuppression of noise, the first power lines are rerouted relative to thesignal lines to reduce noise (step 815). The rerouted line distributionis fed back to step 812 as a revised input for maximizing the widths ofthe first power lines.

At step 818, the plurality of second power lines (operable at a secondelectrical potential, for instance 1.8 V) of the second metal layer isadded to the modeling. The second power lines are modeled to serve asdistributed areas having wide geometries so that self-inductance isminimized. The second power lines merge into a central area, whichserves to support the IC chip. The maximized widths of the second powerlines are used as inputs for step 820, the modeling and simulation ofthe total package.

Additional inputs for step 820 are the structure, thickness, andmaterial characteristics of the insulating layer positioned between thefirst and second metal layers. The goal of the modeling is to providestrong electromagnetic coupling between the signal lines and the firstmetal layer in order to reach a predetermined impedance to ground (forinstance, 50 ohms) and to minimize cross talk between signal lines.

If these goals are not achieved satisfactorily, the layout of signallines and first and second power lines are modified in step 822 and thenew layout is fed back as improved input to the modeling of the totalpackage in step 820. The final output of the electrical modeling isdisplayed in step 824, which ends method 800.

FIG. 9 is a flowchart illustrating an exemplary method 900 forfabricating a high-performance, high I/O ball grid array substrate forIC flip-chip assembly, having two patterned metal layer and oneintermediate insulating layer, according to the teachings of the presentinvention. Method 900 begins at step 902 and proceeds next to step 904where an insulating layer is provided that has a first surface and asecond surface. Suitable materials include polyimides, epoxy glass(FR-4, FR-5, or BT), or other flexible electrically non-conductivematerials; thickness usually in range 70 to 150 μm.

At step 906, the insulating layer of the substrate is patterned to forma plurality of via holes using mechanical drilling or a laser beamtechnique. At step 908, the via holes are filled with metal, such ascopper, or other electrically conductive material, creating a pluralityof electrically conductive vias through the insulating layer of thesubstrate.

At step 910, one of the two metal layers (preferably copper, thicknessbetween 7 to 15 μm) is attached to the first surface of the insulatinglayer (using typically a roll-on process). This metal layer is intendedto provide electrical ground potential in the BGA. The patterning ofthis metal layer, using standard photo-lithographic techniques, to forma plurality of electrically insulated openings intended for outsideelectrical contacts, such as solder balls, is performed at step 912.

At step 914, the other of the two metal layers (preferably copper,thickness between 7 to 15 μm) is attached to the second surface of theinsulating layer (using typically a roll-on process). This metal layeris intended to provide three functions in three patterned portions. Thepatterning of this metal layer in step 916, using standardphoto-lithographic techniques, creates the plurality of signal lines;the plurality of first power lines, providing a specific electricalpotential; and the plurality of second power lines, providing anotherspecific electrical potential. Selected signal and power lines are inelectrical contact with the vias in the insulating layer.

At step 918, insulating protective films are formed over the exposedsurface of the ground layer and over the exposed surfaces of the signaland power lines. At step 920, pluralities of openings are formed in bothinsulating films; these openings are then filled with solderable metal(for instance, copper with gold flash), creating attachment sites foroutside solder balls used in board attach, and for chip solder bumpsused in flip-chip assembly. The fabrication of the BGA substrate is thuscompleted.

In order to finish the fabrication of the BGA package, method 900continues at step 922 by attaching an IC chip to the substrate. The chiphas an active surface including solder bumps. These bumps are adhered tothe plurality of metal-filled openings in the outermost insulating filmprotecting the signal and power lines. The solder reflow typicallyinvolves the temperature of the eutectic tin/lead mixture.

The process flow chart continues at step 924 or, if needed, at step 923.At step 923, any gaps are filled between the substrate and the chip leftvoid after the chip solder bumps have been adhered to the plurality ofopenings in the outermost insulating film protecting the signal andpower lines. As filling material, a polymeric encapsulant is commonlyused made of an epoxy-based precursor filled with silica and anhydrides,requiring elevated temperatures for curing.

At step 924, the chip (more precisely, the passive surface of the chipand its four edge sides) is surrounded with a polymeric encapsulationcompound; preferably, a transfer molding process is used.

Due to the short thermal paths for heat dissipation, the thermalcharacteristics of the BGA of the invention are excellent. If furtherimprovement is required, a heat slug can be attached in step 925; it ispreferably positioned on the outer surface of the cured encapsulationmaterial.

At step 926, solder balls are attached to the plurality of metal-filledopenings in the outermost insulating film protecting the ground layer.This process provides external electrical and mechanical connections tothe BGA package. Generally, the solder balls will be arrayed in arectangular pattern around the periphery of the BGA package; a multitudeof balls may also be positioned in the center of the package. Method 900ends at step 928.

While this invention has been described in reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. As an example, the material of the semiconductor chip maycomprise silicon, silicon germanium, gallium arsenide, or any othersemiconductor material used in manufacturing. As another example, theBGA may have an encapsulation made by overmolding or another technique,or may have no encapsulation of the flip-soldered chip at all. Asanother example, instead of the encapsulation using molding compounds, athermally conductive lead may be attached over the flip-soldered chipfor physical protection and thermal enhancement. As another example, thetwo metal layers may be attached to the surfaces of the insulating layerconcurrently and then patterned individually, rather than being attachedand patterned sequentially. It is therefore intended that the appendedclaims encompass any such modifications or embodiments.

1-22. (canceled)
 23. A computer-implemented method for modeling ahigh-performance, high I/O ball grid array substrate, intended forintegrated circuit flip-chip assembly and having a first and a secondmetal layer and one intermediate insulating layer, all of substantiallyequal areas comprising the steps of: modeling the structure of saidfirst metal layer as electrical ground potential, said layer having aplurality of electrically insulated openings for electrical contacts;modeling the structure of said second metal layer as a plurality ofelectrical signal lines, a plurality of first electrical power linesoperable at a first potential, and a plurality of second electricalpower lines operable at a second potential; configuring said first powerlines so wide that their combined inductances approximate the inductanceof a metal having the size of the total substrate; concurrentlydistributing said first power lines among said signal lines in order toprovide at least minimum inductive coupling between signal and powerlines, thereby obtaining high mutual inductances and minimizingeffective self-inductance; 24-29. (canceled)
 30. A method of fabricatinga packaged integrated circuit, comprising the steps of: providing asubstrate having first and second opposing surfaces; providing aplurality of signal lines, a plurality of first power lines coupleableto a first power source, and a plurality of second power linescoupleable to a second power source, all on said second surface, atleast one of said plurality of signal lines disposed between a pair ofsaid plurality of first power lines, and said signal lines between saidpair of said plurality of first power lines and said pair of saidplurality of first power lines disposed between a pair of said secondpower lines; and providing an integrated circuit chip mounted on saidsubstrate.
 31. The method of claim 30, further including providing saidsignal lines of a first width, said first power lines of a second widthdifferent from said first, and said second power lines of a third widthdifferent from said first and second widths.
 32. The method of claim 31,wherein said third width is wider than said second width, and saidsecond width is wider than said first width.
 33. The method of claim 30,further including the step of providing a ground plane on said firstsurface of said substrate.
 34. A method of fabricating a packagedintegrated circuit, comprising the steps of: providing a substratehaving first and second opposing surfaces, said substrate havingthereon: providing a plurality of groups of lines, said plurality ofgroups of lines including groups of lines of at least three differentwidths disposed on said second surface of said substrate, said groups oflines arranged such that one or more lines in a first group of lines ofa first width are disposed between lines of a second group of lines of asecond width and lines in said second group of lines of said secondwidth are disposed between lines of said third width; and providing anintegrated circuit chip; mounting said chip on said substrate; andcoupling said chip to at least some of said lines.
 35. The method ofclaim 34, wherein said lines of said first width are signal lines, saidlines of said second width are power lines coupled to a first voltagepotential, and said lines of said third width are power lines coupled toa second voltage potential.
 36. The method of claim 34, furthercomprising the step of providing a ground plane on said first surface ofsaid substrate.